1. Technical Field
The invention relates to an integrated circuit (IC) fabrication method, and in particular to a system and method for automatically generating mask layouts for integrated circuits.
2. Description of the Related Art
Advances in the fabrication of ICs, such as progress in the very large scale integration (VLSI) techniques and the resulting miniaturization of ICs, have occurred in recent years from, for example, improved fabrication processes. In the IC fabrication process, the detailed features of an IC are formed by photolithographic projection of mask layouts onto a substrate. Accordingly, detailed and accurate mask generation is important for such IC fabrication processes.
A mask features a geometrical pattern of several layers with areas that are selectively transparent or opaque to a wavelength or band of wavelengths used in a particular photolithographic system. To generate a high performance IC using a corresponding mask, a mask layout is constructed to transform individual components associated with an integrated circuit into the geometrical pattern that achieves the required integrated circuit function as well as satisfying other design criteria such as power consumption, speed, circuit size, minimizing parasitics, etc.
Mask layout generation techniques are known in the art, such as automated/computer-aided methodologies, hand-performed i.e. manual layout methodologies, and combinations of computer-aided and manual techniques.
One such automated technique uses predetermined "standard cells" in a cell library. For a particular process, this library of cells may be created beforehand by a variety of methods, including manual or automatic methods, or a mixture of manual and automatic methods. This library is created once for a particular process, and is then made available for use by many particular IC designs. Each cell in the library is a set of discrete logic functions implemented in mask form. Cells from the cell library are selected to serve as building blocks in constructing an IC. Each cell has an associated cell layout and associated information regarding performance characteristics of the cell; for example, power consumption, speed, etc. A significant advantage of using cell libraries is that each cell is already in mask format in the cell library; i.e. the cell layout is fixed, the transistor sizes are also fixed, which fixes the performance of the transistors in the resulting IC. Thus the library of cells may also contain information characterizing the delay, power consumption, and area of each cell. Like the cell layouts, this information needs to be generated only once for a particular process, and can remain unchanged as it is used by many designs.
For example, in standard cell mask layout methodologies for very large scale integration (VLSI) fabrication, a cell-level netlist, a timing specification, and performance characteristics information are used in selecting cells from the cell library. The netlist is a file or other set of specifications which defines the topological and logical structure of the circuit by listing connections between input and output ports of various cells from the standard cell library. The standard cell method may include procedures to change or revise the netlist in order to increase speed or decrease cell area or power, without changing the logic behavior of the circuit outputs.
The revised netlist and cell outlines from the database, i.e. the specification of the boundaries or physical dimensions of the cell and the input/output (I/O) terminals of a cell, are then input to a place-and-route system which arranges and connects the cells. This placement and these connections, along with the cell layouts, constitute a complete mask layout that implements the cell netlist. The performance and logic of the mask layout may be verified in subsequent steps using the performance characteristics provided for each cell. If the performance is unacceptable, either the place-and-route step is repeated or a new revised netlist is created.
Automated mask layout systems are advantageous to use for large circuits or when a complex mask layout is to be generated in a relatively short period of time. However, automated mask layout systems typically lack the capability to design high performance ICs since there are a limited number of cells from which to generate the mask layout. In addition, since the cell library is fixed, the sizes of individual transistors within a cell may not be adjusted, thus limiting design tradeoffs between power consumption, speed and area.
Manual or "by hand" mask layout permits finer adjustment of transistor sizes in order to achieve higher performance. Transistor sizes in each cell are manually adjusted in accordance with various conditions in the cell's environment, such as load capacitance, relative input arrival times, driving impedance of inputs, and delay allotment for the cell. Mask layout for each cell is created by hand, thus creating a cell library tailored specifically for that circuit and timing specification. Placement and routing of these cells can be done manually or with the aid of automatic place and route tools. Timing simulation and analysis tools may be used to determine whether the timing specification has been met.
Manual mask generation typically allows better sizing of transistors to implement increased IC speed, and to reduce power. However, the amount of time required to manually generate a mask layout is typically high, especially when circuits with large numbers of transistors are required. Especially burdensome is the time required to painstakingly verify that each cell complies with connectivity, transistor size, and mask design rules. In the case of a cell library for an automated layout system, this verification process is amortized over a large number of designs. In the case of manual mask layout, this verification must be done for each design, because each design has its own unique cell library.
Systems combining automated mask layout techniques with manual techniques have generally focused primarily on adding cells designed by hand to the cell library of an automated system or in helping to automatically create, place, and route cells in manual systems. A disadvantage of combined automatic and manual methods is that a large number of manually created special cells is required to significantly improve performance. The combined automatic and manual method therefore is still too time-consuming.
There is a need for a mask layout generation process that combines the performance advantages provided by manual layout methods; i.e. the ability to customize layout to optimize power, performance, etc., with the speed of an automated process to implement not only the requisite elements of the IC but also to generate an overall improved mask layout.